Next HPEC-SI meeting will be May 19/20 at Lincoln.
Please RSVP to kepner@ll.mit.edu. The main goals of
the meeting will be:

-Get concrete proposals on the table for all known
issues with the VSIPL++ specification (see James' minutes).
-See VSIPL++ code examples from our varous demos/evals.
-Start looking forward at the issues a parallel
implementation is bringing up.
-Continue to look at FPGAs.

Regards. -Jeremy

Minutes

Open Issues

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AGENDA:

Wednesday

09:00-09:30 BREAKFAST
09:30-10:00 HPEC-SI Overview (Kepner MIT-LL)
10:00-10:30 Demo walkthrough (Pancoast/Cook LMCO)
10:30-11:00 Demo/eval status (Cottel, Sroka, Emeny) PPT / PDF
11:00-11:30 VSIPL++ implementation status (Oldham/CODESOURCERY)
11:30-12:00 Status of VSIPL++ compilation (Leimbach MSTI)
12:00-01:00 LUNCH
01:00-01:30 VSIPL++ Specification action items status (Lebak)
01:30-02:00 IO Block spec (Campbell GTRI) PDF
02:00-03:00 Discussion
03:00-03:30 BREAK
03:30-04:00 PETE Replacement (Rutledge LINCOLN)
04:00-04:30 Parallel VSIPL++ update (Oldham CODESOURCERY)PPT / PDF
04:30-05:00 Discussion

Thursday
(APPLIED RESEARCH WORKING GROUP)
09:00-09:30 BREAKFAST
09:30-10:00 Recomended Parallel Scoping Mechanism (Rutledge LINCOLN)
10:00-10:30 Parallel Distribution User support functions (Cain, Paavola, Kinney)
10:30-12:00 FPGA / VSIPL++ Strategy Discussion (Lead: Vai)
12:00-01:00 LUNCH

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LOCATION: MIT Lincoln Laboratory, Lexington, MA
Room S2-616
For directions see
http://www.ll.mit.edu/about/visitor.html

ORGANIZERS:

HPEC-SI Development Working Group Co-Chairs
Mark Richards (mark.richards@gtri.gatech.edu)
James Lebak (jlebak@ll.mit.edu)

HPEC-SI Prototypes Working Group Co-Chairs
Bob Bond (rbond@ll.mit.edu)
Ken Flowers (kflowers@mc.com)

HPEC-SI Advisory Board
Jeremy Kepner (kepner@ll.mit.edu)

ATTENDANCE:
Attendance is open to all U.S. Citizens.
If you plan on attending (in person or telecon) please send e-mail to:
kepner@ll.mit.edu