HPEC-SI colleagues,
The next HPEC-SI meeting will be a joint 3 day meeting with the DARPA PCA Morphware Forum. The meeting will be in the Boston area (precise details will be sent out shortly). This joint meeting will allow us to look more deeply into the question of how we can bring VSIPL to PCA and other tiled architectures. A goals and draft agenda are shown below.

Regards. -Jeremy
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GOALS
The main goals of the joint HPEC-SI/PCA meeting will be:
-Present the various approaches for bringing VSIPL
to PCA [Lethin, Campbell, Harrod, Bergman, Lebak]
-Develop a first level trade-off analysis of the
different approaches. [All]
-Decide on what the next steps are. [All]

The main goals of the HPEC-SI part of the meeting will be:
-Review draft of VSIPL++ User's Guide. [Organizer: Campbell,
Contributors: Bergmann, Emeny, Judd, Pancoast, and Sroka]
-Review demos/evaluation plans [LMCO, Rome, SPAWAR, MITRE]
-Review VSIPL++ and parallel VSIPL++ implementation status
[Bergman, Leimbach]
-Review parallel support functions specification [Bergman]
-FPGA IO API status [Leeser/Vai]

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AGENDA (Preliminary):

Tuesday June 21
(DARPA PCA Morphware Forum)
08:30-12:00 Morphware Stable Interface document update/review
-Machine model, Stream VM, User VM, Hardware Architecture Layer
12:00-01:00 Lunch
01:00-03:00 Compile & Execute Homework results
03:00-05:00 Run-time services

Wednesday June 22
(Joint Morphware and HPEC-SI Meeting)
08:30-09:00 BREAKFAST
09:00-09:30 Opening Remarks (Graybill)
09:30-10:00 Morphware Overview (Campbell GT)PPT|PDF
10:00-10:30 HPEC-SI Overview (Kepner MIT-LL)PPT|PDF
10:30-11:00 BREAK
11:00-11:30 Application/Users perspective (Pancoast LMCO)PDF
11:30-12:00 Summary of Different Approaches (Campbell GT)PPT|PDF
12:00-01:00 Lunch
01:00-02:30 Detailed Description of Different Approaches
- VSIPL++ Spec Analysis (Lethin RESERVOIR)PPT|PDF
- R-Stream compiler mapping (Lebak MIT-LL)PPT|PDF
- Automated Parallel Mapping (Travinin MIT-LL) PPT|PDF
- ||VSIPL++ Maps and PCA (Kepner MIT-LL)PPT|PDF
02:30-03:00 BREAK
03:00-04:00 Discussion (Kepner/Richards)
04:00-05:00 FPGA IO API Status and Discussion (Vai/Leeser)

Thursday June 23
(DEMONSTRATION & DEVELOPMENT WORKING GROUPS)
09:00-09:30 BREAKFAST
09:30-10:00 HPEC-SI PCA Action items review
10:00-11:00 Demo/eval status (Cook, Judd, Sroka, Emeny)
11:00-12:00 VSIPL++ Implementation
-VSIPL++ implementation status (Bergmann/ CODESOURCERY)
-Moving Subviews (Bergmann/CODESOURCERY) PPT|PDF
-Parallel VSIPL++ implementation status (Bergmann CODESOURCERY)PPT|PDF
-Parallel VSIPL++ support functions specification (Bergmann CODESOURCERY)PPT|PDF
-VSIPL++: Spec Issues (Myers CODESOURCERY) PPT|PDF
-Status of VSIPL++ compilation (Leimbach VERARI)
-Parallel VSIPL++ cluster status (Campbell (GTRI)PPT|PDF
-VSIPL++ code release status (Campbell GTRI)
12:00-01:00 LUNCH
01:00-02:30 Review/Discussion of VSIPL++ v1.1 items (Lebak MIT-LL)
02:30-03:00 BREAK
03:00-04:00 Review draft of VSIPL++ User's Guide. [Organizer: Campbell,
Contributors: Bergmann, Emeny, Judd, Pancoast, and Sroka]
04:00-05:00 Miscellaneous Items
-Review SAR Benchmark (HPCS SSCA#3) [Meuse MIT-LL]
-Parallel Tasks and CCA

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LOCATION: Boston Area. Details TBA

ORGANIZERS:

HPEC-SI Development Working Group Co-Chairs
Mark Richards (mark.richards@gtri.gatech.edu)
James Lebak (jlebak@ll.mit.edu)

HPEC-SI Prototypes Working Group Co-Chairs
Bob Bond (rbond@ll.mit.edu)
Ken Flowers (kflowers@mc.com)

HPEC-SI Advisory Board
Jeremy Kepner (kepner@ll.mit.edu)

ATTENDANCE:
Attendance is open to all U.S. Citizens.
If you plan on attending (in person or telecon) please send e-mail to:
kepner@ll.mit.edu