HPEC-SI colleagues,
Our next HPEC-SI meeting will be Aug 30/31 at MIT Lincoln Laboratory. Below is a draft agenda. If I am missing something please let me know. If you see your name listed and can't present please let me know. If you are planning on attending please RSVP to kepner@ll.mit.edu.

Regards. -Jeremy

MINUTES

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Tuesday, Aug 30
(DEMONSTRATION & DEVELOPMENT WORKING GROUPS)
09:00-09:30 BREAKFAST
09:30-10:00 HPEC-SI Review & HPEC Preview (Kepner)
10:00-11:00 Demo/eval status (Pancoast, Judd, Sroka, Emeny)PDF
-Cottel API issues list
-Malloc/free overhead in Sourcery VSIPL++ Judd/Cottel PPT | PDF
11:00-12:00 VSIPL++ Implementation
-VSIPL++ implementation status (Bergmann CODESOURCERY)PPT | PDF
-Parallel VSIPL++ implementation status
(Bergmann CODESOURCERY) PDF
-Status of VSIPL++ compilation (Leimbach VERARI)
-Parallel VSIPL++ cluster status (Campbell (GTRI)
-VSIPL++ user's guide status (Campbell GTRI)
12:00-01:00 LUNCH
01:00-01:30 Review of multi-line expression ideas (Lebak MIT-LL)PPT|PDF
01:30-02:30 Review/Discussion of Parallel VSIPL++ functionality (Lebak MIT-LL) PPT|PDF
02:30-03:00 BREAK
03:00-03:30 User defined block proposal (Cain MERCURY)PPT | PDF
04:00-05:00 VSIPL Image Processing (Sacco SKY) PPT | PDF
VSIPro Image

Wednesday, Aug 31
(APPLIED RESEARCH WORKING GROUP & VSIPL FORUM)
09:00-09:30 BREAKFAST
09:30-10:00 Review of VSIPL / PCA plans (Kepner, Harrod)
10:00-11:00 VSIPL++ FIR walkthrough
-Multiline Expression Update (Rutledge) PPT|PDF
-Compiler based approach (Mattson RESERVOIR)
-Template based approach (Kepner, Hoffmann)PPT|PDF
11:00-11:30 FPGA API Update (Leeser, Vai)PPT|PDF
11:30-12:00 Discussion
12:00-01:00 LUNCH
01:00-02:30 VSIPL Forum business
02:30-03:00 BREAK
03:00-05:00 VSIPL Forum business

GOALS
The main goals of the joint HPEC-SI/PCA meeting will be:
-Present the various approaches for bringing VSIPL
to PCA [Lethin, Campbell, Harrod, Bergman, Lebak]
-Develop a first level trade-off analysis of the
different approaches. [All]
-Decide on what the next steps are. [All]

The main goals of the HPEC-SI part of the meeting will be:
-Review draft of VSIPL++ User's Guide. [Organizer: Campbell,
Contributors: Bergmann, Emeny, Judd, Pancoast, andSroka]
-Review demos/evaluation plans [LMCO, Rome, SPAWAR, MITRE]
-Review VSIPL++ and parallel VSIPL++ implementation status
[Bergman, Leimbach]
-Review parallel support functions specification [Bergman]
-FPGA IO API status [Leeser/Vai]

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LOCATION: Boston Area. Details TBA

ORGANIZERS:

HPEC-SI Development Working Group Co-Chairs
Mark Richards (mark.richards@gtri.gatech.edu)
James Lebak (jlebak@ll.mit.edu)

HPEC-SI Prototypes Working Group Co-Chairs
Bob Bond (rbond@ll.mit.edu)
Ken Flowers (kflowers@mc.com)

HPEC-SI Advisory Board
Jeremy Kepner (kepner@ll.mit.edu)

ATTENDANCE:
Attendance is open to all U.S. Citizens.
If you plan on attending (in person or telecon) please send e-mail to:
kepner@ll.mit.edu